Collaboration Accelerates Hyperscale Computing SoC Design for Process Nodes

Cadence Design Systems has optimised the Cadence digital 20.1 full flow for Samsung Foundry’s advanced-process technologies down to 4nm. Within the collaboration, designers can employ the Cadence tools to deliver optimal power, performance, and area and produce accurate, first-pass silicon for hyperscale computing applications.

The solution gives capabilities that are ideal for Samsung’s advanced-process technologies. For example, the iSpatial technology enables a seamless transition from the Genus Synthesis Solution to the Innovus Implementation System employing a common user interface and database. ML capabilities facilitate users to use their existing designs to train the GigaOpt optimisation technology to reduce design margins versus traditional place-and-route flows.

“With the ongoing innovation in hyperscale computing and autonomous driving, there is ever-increasing demand for HPC capacity,” said Sangyun Kim, vice president of the Foundry Design Technology Team at Samsung Electronics. “By combining the latest Samsung Foundry advanced-process nodes with the Cadence 20.1 digital full flow, our customers can achieve their design goals quickly and efficiently.”

“The newly optimised Cadence digital flow makes it much simpler for customers to achieve PPA targets using Samsung Foundry’s advanced process technologies,” said Michael Jackson, corporate vice president, R&D in the Digital & Signoff Group at Cadence. “By expanding upon our longstanding collaboration with Samsung Foundry, designers can rapidly adopt Samsung Foundry’s validated HPC methodologies to deliver exceptional silicon performance on time.”

0

No Comments

No comments yet

Leave a Reply

Your email address will not be published. Required fields are marked *